alpha (4836B)
1 // Alpha support 2 3 defn acidinit() // Called after all the init modules are loaded 4 { 5 bplist = {}; 6 bpfmt = 'X'; 7 8 srcpath = { 9 "./", 10 "/sys/src/libc/port/", 11 "/sys/src/libc/9sys/", 12 "/sys/src/libc/alpha/" 13 }; 14 15 srcfiles = {}; // list of loaded files 16 srctext = {}; // the text of the files 17 } 18 19 defn stk() // trace 20 { 21 _stk(*PC, *SP, linkreg(0), 0); 22 } 23 24 defn lstk() // trace with locals 25 { 26 _stk(*PC, *SP, linkreg(0), 1); 27 } 28 29 defn gpr() // print general purpose registers 30 { 31 print("R0\t", *R0, "\n"); 32 print("R1\t", *R1, " R2\t", *R2, " R3\t", *R3, "\n"); 33 print("R4\t", *R4, " R5\t", *R5, " R6\t", *R6, "\n"); 34 print("R7\t", *R7, " R8\t", *R8, " R9\t", *R9, "\n"); 35 print("R10\t", *R10, " R11\t", *R11, " R12\t", *R12, "\n"); 36 print("R13\t", *R13, " R14\t", *R14, " R15\t", *R15, "\n"); 37 print("R16\t", *R16, " R17\t", *R17, " R18\t", *R18, "\n"); 38 print("R19\t", *R19, " R20\t", *R20, " R21\t", *R21, "\n"); 39 print("R22\t", *R22, " R23\t", *R23, " R24\t", *R24, "\n"); 40 print("R25\t", *R25, " R26\t", *R26, " R27\t", *R27, "\n"); 41 print("R28\t", *R28, " R29\t", *R29, " R30\t", *SP\Y, "\n"); 42 } 43 44 defn fpr() 45 { 46 print("F0\t", *fmt(F0, 'G'), "\tF1\t", *fmt(F1, 'G'), "\n"); 47 print("F2\t", *fmt(F2, 'G'), "\tF3\t", *fmt(F3, 'G'), "\n"); 48 print("F4\t", *fmt(F4, 'G'), "\tF5\t", *fmt(F5, 'G'), "\n"); 49 print("F6\t", *fmt(F6, 'G'), "\tF7\t", *fmt(F7, 'G'), "\n"); 50 print("F8\t", *fmt(F8, 'G'), "\tF9\t", *fmt(F9, 'G'), "\n"); 51 print("F10\t", *fmt(F10, 'G'), "\tF11\t", *fmt(F11, 'G'), "\n"); 52 print("F12\t", *fmt(F12, 'G'), "\tF13\t", *fmt(F13, 'G'), "\n"); 53 print("F14\t", *fmt(F14, 'G'), "\tF15\t", *fmt(F15, 'G'), "\n"); 54 print("F16\t", *fmt(F16, 'G'), "\tF17\t", *fmt(F17, 'G'), "\n"); 55 print("F18\t", *fmt(F18, 'G'), "\tF19\t", *fmt(F19, 'G'), "\n"); 56 print("F20\t", *fmt(F20, 'G'), "\tF21\t", *fmt(F21, 'G'), "\n"); 57 print("F22\t", *fmt(F22, 'G'), "\tF23\t", *fmt(F23, 'G'), "\n"); 58 print("F24\t", *fmt(F24, 'G'), "\tF25\t", *fmt(F25, 'G'), "\n"); 59 print("F26\t", *fmt(F26, 'G'), "\tF27\t", *fmt(F27, 'G'), "\n"); 60 print("F28\t", *fmt(F28, 'G'), "\tF29\t", *fmt(F29, 'G'), "\n"); 61 print("F30\t", *fmt(F30, 'G'), "\tF31\t", *fmt(F31, 'G'), "\n"); 62 } 63 64 defn spr() // print special processor registers 65 { 66 local pc, link, cause; 67 68 pc = *PC; 69 print("PC\t", pc, " ", fmt(pc, 'a'), " "); 70 pfl(pc); 71 72 link = *R26; 73 print("SP\t", *SP, "\tLINK\t", link, " ", fmt(link, 'a'), " "); 74 pfl(link); 75 76 cause = *TYPE; 77 print("STATUS\t", *STATUS, "\tTYPE\t", cause, " ", reason(cause), "\n"); 78 print("A0\t", *A0, " A1\t", *A1, " A2\t", *A2, "\n"); 79 } 80 81 defn regs() // print all registers 82 { 83 spr(); 84 gpr(); 85 } 86 87 defn pstop(pid) 88 { 89 local l, pc; 90 91 pc = *PC; 92 93 print(pid,": ", reason(*TYPE), "\t"); 94 print(fmt(pc, 'a'), "\t", fmt(pc, 'i'), "\n"); 95 96 if notes then { 97 if notes[0] != "sys: breakpoint" then { 98 print("Notes pending:\n"); 99 l = notes; 100 while l do { 101 print("\t", head l, "\n"); 102 l = tail l; 103 } 104 } 105 } 106 } 107 108 sizeofUreg = 296; 109 aggr Ureg 110 { 111 'W' 0 type; 112 'W' 8 a0; 113 'W' 16 a1; 114 'W' 24 a2; 115 'W' 32 r0; 116 'W' 40 r1; 117 'W' 48 r2; 118 'W' 56 r3; 119 'W' 64 r4; 120 'W' 72 r5; 121 'W' 80 r6; 122 'W' 88 r7; 123 'W' 96 r8; 124 'W' 104 r9; 125 'W' 112 r10; 126 'W' 120 r11; 127 'W' 128 r12; 128 'W' 136 r13; 129 'W' 144 r14; 130 'W' 152 r15; 131 'W' 160 r19; 132 'W' 168 r20; 133 'W' 176 r21; 134 'W' 184 r22; 135 'W' 192 r23; 136 'W' 200 r24; 137 'W' 208 r25; 138 'W' 216 r26; 139 'W' 224 r27; 140 'W' 232 r28; 141 { 142 'W' 240 r30; 143 'W' 240 usp; 144 'W' 240 sp; 145 }; 146 'W' 248 status; 147 'W' 256 pc; 148 'W' 264 r29; 149 'W' 272 r16; 150 'W' 280 r17; 151 'W' 288 r18; 152 }; 153 154 defn 155 Ureg(addr) { 156 complex Ureg addr; 157 print(" type ", addr.type, "\n"); 158 print(" a0 ", addr.a0, "\n"); 159 print(" a1 ", addr.a1, "\n"); 160 print(" a2 ", addr.a2, "\n"); 161 print(" r0 ", addr.r0, "\n"); 162 print(" r1 ", addr.r1, "\n"); 163 print(" r2 ", addr.r2, "\n"); 164 print(" r3 ", addr.r3, "\n"); 165 print(" r4 ", addr.r4, "\n"); 166 print(" r5 ", addr.r5, "\n"); 167 print(" r6 ", addr.r6, "\n"); 168 print(" r7 ", addr.r7, "\n"); 169 print(" r8 ", addr.r8, "\n"); 170 print(" r9 ", addr.r9, "\n"); 171 print(" r10 ", addr.r10, "\n"); 172 print(" r11 ", addr.r11, "\n"); 173 print(" r12 ", addr.r12, "\n"); 174 print(" r13 ", addr.r13, "\n"); 175 print(" r14 ", addr.r14, "\n"); 176 print(" r15 ", addr.r15, "\n"); 177 print(" r19 ", addr.r19, "\n"); 178 print(" r20 ", addr.r20, "\n"); 179 print(" r21 ", addr.r21, "\n"); 180 print(" r22 ", addr.r22, "\n"); 181 print(" r23 ", addr.r23, "\n"); 182 print(" r24 ", addr.r24, "\n"); 183 print(" r25 ", addr.r25, "\n"); 184 print(" r26 ", addr.r26, "\n"); 185 print(" r27 ", addr.r27, "\n"); 186 print(" r28 ", addr.r28, "\n"); 187 print("_12_ {\n"); 188 _12_(addr+240); 189 print("}\n"); 190 print(" status ", addr.status, "\n"); 191 print(" pc ", addr.pc, "\n"); 192 print(" r29 ", addr.r29, "\n"); 193 print(" r16 ", addr.r16, "\n"); 194 print(" r17 ", addr.r17, "\n"); 195 print(" r18 ", addr.r18, "\n"); 196 }; 197 198 defn linkreg(addr) 199 { 200 complex Ureg addr; 201 return addr.r26\X; 202 } 203 204 print(acidfile); 205